Quoting Dmitry Osipenko (2019-04-19 04:42:26) > Initially Common Clock Framework isn't aware of the clock-enable status, > this results in enabling of clocks that were enabled by bootloader. This > is not a big deal for a regular clock-gates, but for PLL's it may have > some unpleasant consequences. Thus re-enabling PLLX (the main CPU parent > clock) may result in extra long period of PLL re-locking. > > Acked-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx> > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> > --- Applied to clk-next
