03.04.2019 11:41, Thierry Reding пишет: > On Thu, Mar 07, 2019 at 01:50:07AM +0300, Dmitry Osipenko wrote: >> Both Tegra30 and Tegra114 have 4 ASID's and the corresponding bitfield of >> the TLB_FLUSH register differs from later Tegra generations that have 128 >> ASID's. >> >> In a result the PTE's are now flushed correctly from TLB and this fixes >> problems with graphics (randomly failing tests) on Tegra30. >> >> Cc: stable <stable@xxxxxxxxxxxxxxx> >> Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> >> --- >> drivers/iommu/tegra-smmu.c | 25 ++++++++++++++++++------- >> 1 file changed, 18 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c >> index 5182c7d6171e..8d30653cd13a 100644 >> --- a/drivers/iommu/tegra-smmu.c >> +++ b/drivers/iommu/tegra-smmu.c >> @@ -102,7 +102,6 @@ static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) >> #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) >> #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) >> #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) >> -#define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24) > > Given that the same operation is repeated three times below, it might > have been worth to fold the conditional into the macro. That'd require > the macro to take an smmu parameter, but would otherwise leave the > individual instances shorter. I had that variant initially and the result felt more clumsy to me. > But either way, the fix is good, so: > > Acked-by: Thierry Reding <treding@xxxxxxxxxx> > Thanks
