> On Tue, Mar 26, 2019 at 10:56:45PM -0700, Sowjanya Komatineni wrote: > > With SW CS, during transfer completion CS is de-asserted by writing > > the default command1 register value to SPI_COMMAND1 register. With > > this both mode and CS state are set at the same time and if current > > transfer mode is different to default SPI mode and if mode change > > happens prior to CS de-assert, clock polarity can change while CS is > > active before transfer finishes. > > This is a bug fix so I'd expect it to be much earlier in the series before any of the new features. Thanks Mark. Will change order as per your feedback in next version of patch series. I see you have applied some patches in V1 series so should I re-send again those as well along with feedback changes in next version or just only the patches that are not applied.
