The xavier CPU architecture includes 8 CPU cores organized in
4 clusters. Add cpu-map data for topology initialization, this
fixes the topology information in
/sys/devices/system/cpu/cpu[n]/topology
Signed-off-by: Bo Yan <byan@xxxxxxxxxx>
---
V3: Replaced phandles with full path to CPU node
V2: remove cache nodes, add topology data only
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 42 ++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 6dfa1ca..708d20c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -870,6 +870,48 @@
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&{/cpus/cpu@0}>;
+ };
+
+ core1 {
+ cpu = <&{/cpus/cpu@1}>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&{/cpus/cpu@2}>;
+ };
+
+ core1 {
+ cpu = <&{/cpus/cpu@3}>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&{/cpus/cpu@4}>;
+ };
+
+ core1 {
+ cpu = <&{/cpus/cpu@5}>;
+ };
+ };
+
+ cluster3 {
+ core0 {
+ cpu = <&{/cpus/cpu@6}>;
+ };
+
+ core1 {
+ cpu = <&{/cpus/cpu@7}>;
+ };
+ };
+ };
+
cpu@0 {
compatible = "nvidia,tegra194-carmel", "arm,armv8";
device_type = "cpu";
--
2.7.4
