On Fri, Jan 25, 2019 at 11:00:57AM +0100, Thierry Reding wrote: > From: Thierry Reding <treding@xxxxxxxxxx> > > The SOR has a crossbar that can map each lane of the SOR to each of the > SOR pads. The mapping is usually the same across designs for a specific > SoC generation, but every now and then there's a design that doesn't. > > Allow the crossbar configuration to be specified in device tree to make > it possible to support these designs. > > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> > --- > .../bindings/display/tegra/nvidia,tegra20-host1x.txt | 3 +++ > 1 file changed, 3 insertions(+) Hi Rob, any comments on this? Thanks, Thierry > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > index 593be44a53c9..9999255ac5b6 100644 > --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > @@ -238,6 +238,9 @@ of the following host1x client modules: > - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection > - nvidia,edid: supplies a binary EDID blob > - nvidia,panel: phandle of a display panel > + - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane > + of the SOR, identified by the cell's index, is mapped via the crossbar to > + the pad specified by the cell's value. > > Optional properties when driving an eDP output: > - nvidia,dpaux: phandle to a DispayPort AUX interface > -- > 2.19.1 >
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