On 07/01/2019 03:28, Joseph Lo wrote: > The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit > timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived > from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock > (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic, > or watchdog interrupts. > > Cc: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx> > Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx> > Cc: linux-kernel@xxxxxxxxxxxxxxx > Cc: devicetree@xxxxxxxxxxxxxxx > Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx> > --- > .../bindings/timer/nvidia,tegra210-timer.txt | 25 +++++++++++++++++++ > 1 file changed, 25 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt > > diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt > new file mode 100644 > index 000000000000..ba511220a669 > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt > @@ -0,0 +1,25 @@ > +NVIDIA Tegra210 timer > + > +The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit > +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived > +from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock > +(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic, > +or watchdog interrupts. > + > +Required properties: > +- compatible : "nvidia,tegra210-timer". > +- reg : Specifies base physical address and size of the registers. > +- interrupts : A list of 4 interrupts; one per each of TMR10 through TMR13. Why do we only add the interrupts for TMR10 - TMR13? What about the others? Cheers Jon -- nvpublic
