Re: [PATCH 09/19] clk: tegra: dfll: add CVB tables for Tegra210

[Joseph Lo <josephl@xxxxxxxxxx>]

On 12/7/18 10:39 PM, Jon Hunter wrote:
> On 04/12/2018 09:25, Joseph Lo wrote:
> > Add CVB tables with different chip characterization, so that we can
> > generate the customize OPP table that suitable for different chips with
> > different SKUs.
> >
> > Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx>
> > ---
> >   drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 426 +++++++++++++++++++++
> >   drivers/clk/tegra/cvb.h                    |   1 +
> >   2 files changed, 427 insertions(+)
> >
> > diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> > index 071a5c674832..bc1358d8084b 100644
> > --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> > +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
> > @@ -88,6 +88,421 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = {
> >   	},
> >   };
> >   
snip.
> >   
> > diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h
> > index bcf15a089b93..91a1941c21ef 100644
> > --- a/drivers/clk/tegra/cvb.h
> > +++ b/drivers/clk/tegra/cvb.h
> > @@ -41,6 +41,7 @@ struct cvb_cpu_dfll_data {
> >   	u32 tune0_low;
> >   	u32 tune0_high;
> >   	u32 tune1;
> > +	unsigned int tune_high_min_millivolts;
>
> Where is this actually used?

It's just part of the initial CVB table. We don't have the dynamic 
tunning support yet that will use this tune parameter for output freq 
tunning. It's on my plan of the next series for DFLL enhancement.

Should I remove that from the table?

Thanks,
Joseph