On 04/12/2018 09:25, Joseph Lo wrote:
> When generating the OPP table, the voltages are round down with the
> alignment from the regulator. The alignment should be applied for
> voltages look up as well.
>
> Based on the work of Penny Chiu <pchiu@xxxxxxxxxx>.
>
> Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx>
> ---
> drivers/clk/tegra/clk-dfll.c | 26 +++++++++++++++-----------
> 1 file changed, 15 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
> index c294a2989f31..4a943c136d4d 100644
> --- a/drivers/clk/tegra/clk-dfll.c
> +++ b/drivers/clk/tegra/clk-dfll.c
> @@ -804,17 +804,17 @@ static void dfll_init_out_if(struct tegra_dfll *td)
> static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate)
> {
> struct dev_pm_opp *opp;
> - int i, uv;
> + int i, align_volt;
>
> opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
> if (IS_ERR(opp))
> return PTR_ERR(opp);
>
> - uv = dev_pm_opp_get_voltage(opp);
This returns an unsigned long.
> + align_volt = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv;
Nit-pick, the 'align_volt' variable does not contain an actual voltage
but a step index. So maybe consider renaming this 'align_step'. And the
same for other places in this change.
Cheers
Jon
--
nvpublic
