On 04/12/2018 09:25, Joseph Lo wrote:
> The cpu_lp clock property is only needed when the CPUfreq driver
> supports CPU cluster switching. But it was not a design for this driver
> and it didn't handle that as well. So removing this property.
>
> Cc: devicetree@xxxxxxxxxxxxxxx
> Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx>
> ---
> .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
> index 031545a29caf..03196d5ea515 100644
> --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
> +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
> @@ -9,7 +9,6 @@ Required properties:
> See ../clocks/clock-bindings.txt for details.
> - clock-names: Must include the following entries:
> - cpu_g: Clock mux for the fast CPU cluster.
> - - cpu_lp: Clock mux for the low-power CPU cluster.
> - pll_x: Fast PLL clocksource.
> - pll_p: Auxiliary PLL used during fast PLL rate changes.
> - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
> @@ -30,11 +29,10 @@ cpus {
> reg = <0>;
>
> clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
> - <&tegra_car TEGRA124_CLK_CCLK_LP>,
> <&tegra_car TEGRA124_CLK_PLL_X>,
> <&tegra_car TEGRA124_CLK_PLL_P>,
> <&dfll>;
> - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
> + clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
> clock-latency = <300000>;
> };
>
>
Acked-by: Jon Hunter <jonathanh@xxxxxxxxxx>
Cheers
Jon
--
nvpublic
