On Tue, Dec 04, 2018 at 05:25:32PM +0800, Joseph Lo wrote:
> The Tegra124 cpufreq driver works only with DFLL clock, which is a
> hardware-based frequency/voltage controller. The driver doesn't need to
> control the regulator itself. Hence remove that.
>
I think this is required for DFLL controlled I2C regulators because the
regulator is queried for voltage selectors and I2C slave ID?
Peter.
> Cc: devicetree@xxxxxxxxxxxxxxx
> Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx>
> ---
> .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
> index b1669fbfb740..031545a29caf 100644
> --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
> +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
> @@ -13,7 +13,6 @@ Required properties:
> - pll_x: Fast PLL clocksource.
> - pll_p: Auxiliary PLL used during fast PLL rate changes.
> - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
> -- vdd-cpu-supply: Regulator for CPU voltage
>
> Optional properties:
> - clock-latency: Specify the possible maximum transition latency for clock,
> @@ -37,7 +36,6 @@ cpus {
> <&dfll>;
> clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
> clock-latency = <300000>;
> - vdd-cpu-supply: <&vdd_cpu>;
> };
>
> <...>
> --
> 2.19.2
>
