Enable DFLL clock for Jetson TX1 platform.
Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx>
---
.../boot/dts/nvidia/tegra210-p2371-2180.dts | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 37e3c46e753f..53f497c2b3ff 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -78,4 +78,24 @@
};
};
};
+
+ clock@70110000 {
+ status = "okay";
+ nvidia,pwm-to-pmic;
+ nvidia,init-uv = <1000000>;
+ nvidia,align-offset-uv = <708000>;
+ nvidia,align-step-uv = <19200>;
+ nvidia,sample-rate = <25000>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,cf = <6>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+ nvidia,idle-override;
+ nvidia,one-shot-calibrate;
+ nvidia,pwm-period = <2500>; /* 2.5us */
+ pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
+ pinctrl-0 = <&dvfs_pwm_active_state>;
+ pinctrl-1 = <&dvfs_pwm_inactive_state>;
+ };
};
--
2.19.2
