Hi Jon & all On 10/26/2018 04:48 PM, Jon Hunter wrote: > Hi Georgi, > > On 22/10/2018 17:36, Georgi Djakov wrote: >> Hello Jon and Dmitry, >> >> I am working on API [1] which allows consumer drivers to express their >> bandwidth needs between various SoC components - for example from CPU to >> memory, from video decoders and DSPs etc. Then the system can aggregate >> the needed bandwidth between the components and set the on-chip >> interconnects to the most optimal power/performance profile. >> >> I was wondering if there is any DVFS management related to interconnects >> on Tegra platforms, as my experience is mostly with Qualcomm hardware. >> The reason i am asking is that i want to make sure that the API design >> and the DT bindings would work or at least do not conflict with how DFVS >> is done on Tegra platforms. So do you know if there is any bus clock >> scaling or dynamic interconnect configuration done by firmware or >> software in downstream kernels? >> >> Thanks, >> Georgi >> >> [1]. >> > > The downstream kernels do have a bandwidth manager driver for managing > the memory controller speed/latency, however, I am not sure about the > actual internal interconnect itself. > > Adding the linux-tegra mailing list for visibility. > Thanks! This sounds interesting! I looked at some 4.9 kernel and found references to some bwmgr functions, which look like they can do some dynamic bandwidth scaling. Is the full implementation available publicly? Are there any plans on upstreaming this? BR, Georgi
