Calling clk_set_rate or clk_round_rate will lock up the kernel when the rate is zero. This avoids the infinite loop and uses a slightly more optimized p divider calculation. Signed-off-by: ryang <decatf@xxxxxxxxx> --- drivers/clk/tegra/clk-pll.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 830d1c87fa7c..17a058c3bbc1 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -582,9 +582,8 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, } /* Raise VCO to guarantee 0.5% accuracy */ - for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; - cfg->output_rate <<= 1) - p_div++; + p_div = rate ? fls((200 * cfreq) / rate) : 0; + cfg->output_rate = rate << p_div; cfg->m = parent_rate / cfreq; cfg->n = cfg->output_rate / cfreq; -- 2.17.1
