On 8/31/18 12:29 PM, Peter De Schrijver wrote: > On Thu, Aug 30, 2018 at 09:42:10PM +0300, Dmitry Osipenko wrote: >> Currently all PLL's on Tegra20 use a hardcoded delay despite of having >> a lock-status bit. The lock-status polling was disabled ~7 years ago >> because PLLE was failing to lock and was a suspicion that other PLLs >> might be faulty too. Other PLLs are okay, hence enable the lock-status >> polling for them. This reduces delay of any operation that require PLL >> to lock. >> >> Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> >> --- >> >> Changelog: >> >> v2: Don't enable polling for PLLE as it known to not being able to lock. >> > > This isn't correct. The lock bit of PLLE can declare lock too early, but the > PLL itself does lock. Indeed, it locks but can't be polled for the lock-status as it doesn't have the lock-status bit. Do you want me to adjust the commit description or it is fine as is? It is also a bit odd that PLLE has "lock_delay = 0", is it correct?
