On 23/01/18 09:22, Peter De Schrijver wrote:
> To ensure writes to clock registers have properly propagated through the
> clock control logic and state machines, we need to ensure the writes have
> been posted in the registers and wait for 1us after that.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
> ---
> drivers/clk/tegra/clk.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 3b2763d..ba7e20e 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -812,4 +812,11 @@ static inline struct clk *tegra_clk_register_emc(void __iomem *base,
> u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
> int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
>
> +/* Combined read fence with delay */
> +#define fence_udelay(delay, reg) \
> + do { \
> + readl(reg); \
> + udelay(delay); \
> + } while (0)
> +
> #endif /* TEGRA_CLK_H */
Not sure we need to pass the delay here if it is always 1us per the
description. But it is fine with me so ...
Acked-by: Jon Hunter <jonathanh@xxxxxxxxxx>
Cheers
Jon
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