On Tue, Jan 02, 2018 at 06:32:11PM +0000, Jon Hunter wrote:
>
> On 20/12/17 18:15, Thierry Reding wrote:
> > On Wed, Dec 20, 2017 at 11:32:23AM +0000, Guillaume Tucker wrote:
> >> When neither HDMI nor DP is supported such as on the tegra124, the
> >> sor->clk_out is not initialised and remains NULL. In this case, the
> >> parent clock can't be assigned to it so revert to the previous
> >> behaviour of assigning it to the main sor->clk instead.
> >>
> >> This fixes a kernel hang on tegra124 and should also affect tegra210
> >> as they both don't support HDMI and DP. Tested on tegra124 only.
> >>
> >> Fixes: e1335e2f0cfc ("drm/tegra: sor: Reimplement pad clock")
> >> Signed-off-by: Guillaume Tucker <guillaume.tucker@xxxxxxxxxxxxx>
> >> CC: Thierry Reding <treding@xxxxxxxxxx>
> >> ---
> >> drivers/gpu/drm/tegra/sor.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > How about just the below instead? It's one more line than your patch,
> > but it will automatically handle all occurrences of clk_out properly.
> >
> > --- >8 ---
> > diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
> > index f6313c4d612e..4be9edf9c6fe 100644
> > --- a/drivers/gpu/drm/tegra/sor.c
> > +++ b/drivers/gpu/drm/tegra/sor.c
> > @@ -3047,6 +3047,8 @@ static int tegra_sor_probe(struct platform_device *pdev)
> > name, err);
> > goto remove;
> > }
> > + } else {
> > + sor->clk_out = sor->clk;
> > }
> >
> > sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
> > --- >8 ---
> >
> > That said, I suspect the SOR might be compatible from a clock point of
> > view with later versions and perhaps we just didn't implement clocks
> > correctly back in the Tegra124 timeframe.
> >
> > Maybe Peter knows.
>
> So the above change from Thierry works for me and we need this for v4.15
> (otherwise nyan-big does not boot) so you can have my ...
>
> Tested-by: Jon Hunter <jonathanh@xxxxxxxxxx>
>
> However, would be good to have Peter's ACK, especially seeing that
> Tegra210 sor0 does not support HDMI and DP. So we need to make sure this
> is correct for Tegra210 as well (although I have not seen any
> regressions for Tegra210).
There are no Tegra210 boards with eDP or LVDS support, which are the
only setups that are impacted by this.
I've sent out the above as a proper patch. I'll submit this for a late
fixes pull request.
Thierry
Attachment:
signature.asc
Description: PGP signature
