On Tue, Dec 19, 2017 at 11:04:25PM +0000, Jon Hunter wrote:
>
> On 16/11/17 14:29, Peter De Schrijver wrote:
> > To ensure writes to clock registers have properly propagated through the
> > clock control logic and state machines, we need to ensure the writes have
> > been posted in the registers and wait for 1us after that.
>
> Is this is all cases or just for the SLCG?
>
> > Signed-off-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
> > ---
> > drivers/clk/tegra/clk.h | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> > index 872f118..d5badbe 100644
> > --- a/drivers/clk/tegra/clk.h
> > +++ b/drivers/clk/tegra/clk.h
> > @@ -809,4 +809,11 @@ static inline struct clk *tegra_clk_register_emc(void __iomem *base,
> > u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
> > int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
> >
> > +/* Combined read fence with delay */
> > +#define fence_udelay(delay, reg) \
> > + do { \
> > + readl(reg); \
> > + udelay(delay); \
> > + } while(0)
> > +
> > #endif /* TEGRA_CLK_H */
>
> Do we plan to use this else-where or just for this WAR? I am wondering
> if it should just go in the Tegra210 clock file.
>
Eventually yes. But I didn't want to add too many things to this series.
Peter.
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