>>>>> "Peter" == Peter Chubb <Peter.Chubb@xxxxxxxxxxxxxxx> writes:
>>>>> "Simon" == Simon Glass <sjg@xxxxxxxxxxxx> writes:
Simon> Oh dear. I cannot find my board but will see if I can repeat
Simon> this on a beaver.
Peter> If there's any additional logging you'd like me to collect on
Peter> the Jetson, let me know.
I tried to reproduce this this morning. Today, even trying to exec
the U-Boot without flashing fails.
So,
./tegra-uboot-flasher exec jetson-tk1
with a current u-boot gives an inoperative eMMC.
In the boot header I see:
U-Boot 2017.05-00769-g0e513e788f (Jun 08 2017 - 09:26:27 +1000)
TEGRA124
Model: NVIDIA Jetson TK1
Board: NVIDIA Jetson TK1
DRAM: 2 GiB
MMC: sdhci@700b0400: 1, sdhci@700b0600: 0
Then:
Tegra124 (Jetson TK1) # mmc rescan
tegra_mmc_send_cmd_bounced: MMC Timeout
Interrupt status 0x00000001
Interrupt status enable 0xffff003b
Interrupt signal enable 0xffff0002
Present status 0x01fb02f6
mmc_init: -1, time 8042
Peter C
--
Dr Peter Chubb Tel: +61 2 9490 5852 http://ts.data61.csiro.au/
Trustworthy Systems Group Data61 (formerly NICTA)--
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