On Tue, Mar 14, 2017 at 04:12:49PM +0200, Peter De Schrijver wrote: > In normal operation pll_u is under hardware control and has a fixed rate of > 480MHz. Hardware will turn on pll_u on whenever any of the XUSB > powerdomains is on. From a software point of view we model this is if pll_u > is always on using a fixed rate clock. However the bootloader might or > might not have configured pll_u this way. So we will check the current > state of pll_u at boot and reconfigure it if required. > > There are 3 possiblities at kernel boot: > 1) pll_u is under hardware control: do nothing > 2) pll_u is under hardware control and enabled: enable hardware control > 3) pll_u is disabled: enable pll_u and enable hardware control > > In all cases we also check if UTMIPLL is under hardware control at boot > and configure it for hardware control if that is not the case. > The same is done during SC7 resume. > > Thanks to Joseph Lo <josephl@xxxxxxxxxx> for bug fixes. > > Signed-off-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx> > --- > drivers/clk/tegra/clk-pll.c | 174 ----------------------- > drivers/clk/tegra/clk-tegra210.c | 295 ++++++++++++++++++++++++++++++++++++--- > 2 files changed, 272 insertions(+), 197 deletions(-) Applied, thanks. Do you think this actually fixes a bug? We've had a long standing issue with booting Debian on a Jetson TX1 which is due to some USB related PLL failing to lock. This sounds like it could fix that particular issue. Thierry
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