On 08/24, Thierry Reding wrote: > From: Vince Hsu <vinceh@xxxxxxxxxx> > > Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when > the DIS power domain is during up-powergating process but the clamp to this > domain is not removed yet. That causes a timeout and aborts the power > sequence, although the PLLD/PLLD2 has already locked. To remove the false > alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the > clocks as locked. > > Signed-off-by: Vince Hsu <vinceh@xxxxxxxxxx> > Tested-by: Jonathan Hunter <jonathanh@xxxxxxxxxx> > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> > --- Applied to clk-fixes -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
