On Tue, Jul 19, 2016 at 03:36:32PM +0200, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@xxxxxxxxx>
>
> Add TEGRA20_CLK_NOR to init tabel and set a "sane" default rate.
>
> Signed-off-by: Mirza Krak <mirza.krak@xxxxxxxxx>
> ---
> drivers/clk/tegra/clk-tegra20.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index 837e5cb..aefc044 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
> { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
> { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
> { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
> + { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 86500000, 0 },
Yay for inconsistent naming in the hardware. It would've been nice if
this clock was called GMI. Oh well...
Could you perhaps explain in the commit message why 86.5 MHz is a sane
default? I'm totally unfamiliar with this controller, so maybe it's
self-explanatory, but it seems a rather odd value for a clock frequency.
Thierry
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