On 6/21/2016 11:30 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@xxxxxxxxxx>
>
> The timer clock feeds the timer block, which, among other things, is
> used to drive the SOR lane sequencer. Since the Tegra timer driver is
> not enabled on 64-bit ARM, nothing currently claims that clock and it
> gets disabled by the common clock framework at late_init time.
>
> Given the non-obvious dependencies, the timer clock can be considered
> a critical part of the SoC infrastructure, requiring its clock source
> to be always on.
>
> Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
> ---
> drivers/clk/tegra/clk-tegra-periph.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
> index af85c8aeaf5a..4ce4e7fb1124 100644
> --- a/drivers/clk/tegra/clk-tegra-periph.c
> +++ b/drivers/clk/tegra/clk-tegra-periph.c
> @@ -792,7 +792,7 @@ static struct tegra_periph_init_data periph_clks[] = {
>
> static struct tegra_periph_init_data gate_clks[] = {
> GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
> - GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0),
> + GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
> GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
> GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
> GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
>
Acked-by: Rhyland Klein <rklein@xxxxxxxxxx>
--
nvpublic
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