On Fri, Apr 22, 2016 at 06:31:03PM +0800, Penny Chiu wrote:
> The DVCO present in the DFLL IP block has a separate reset line,
> exposed via the CAR IP block. This reset line is asserted upon SoC
> reset. Unless something (such as the DFLL driver) deasserts this
> line, the DVCO will not oscillate, although reads and writes to the
> DFLL IP block will complete.
>
> Signed-off-by: Penny Chiu <pchiu@xxxxxxxxxx>
> ---
> drivers/clk/tegra/clk-tegra210.c | 68 ++++++++++++++++++++++++++++++++
> include/dt-bindings/reset/tegra210-car.h | 12 ++++++
> 2 files changed, 80 insertions(+)
> create mode 100644 include/dt-bindings/reset/tegra210-car.h
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index d3709b1..3d70b38 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -24,6 +24,7 @@
> #include <linux/export.h>
> #include <linux/clk/tegra.h>
> #include <dt-bindings/clock/tegra210-car.h>
> +#include <dt-bindings/reset/tegra210-car.h>
>
> #include "clk.h"
> #include "clk-id.h"
> @@ -39,6 +40,9 @@
> #define CLK_SOURCE_CSITE 0x1d4
> #define CLK_SOURCE_EMC 0x19c
>
> +#define RST_DFLL_DVCO 0x2f4
> +#define DVFS_DFLL_RESET_SHIFT 0
It'd be more idiomatic to make this:
#define DVFS_DFLL_RESET (1 << 0)
and use that below instead of hard-coding the 1 << and shifting by the
define.
> +
> #define PLLC_BASE 0x80
> #define PLLC_OUT 0x84
> #define PLLC_MISC0 0x88
> @@ -2781,6 +2785,68 @@ static void __init tegra210_clock_apply_init_table(void)
> }
>
> /**
> + * tegra210_car_barrier - wait for pending writes to the CAR to complete
> + *
> + * Wait for any outstanding writes to the CAR MMIO space from this CPU
> + * to complete before continuing execution. No return value.
> + */
> +static void tegra210_car_barrier(void)
> +{
> + readl_relaxed(clk_base + RST_DFLL_DVCO);
> +}
If you use the plain readl() and writel() functions, do you still need
the barrier? Or is there actually a requirement from the hardware to
flush writes by reading from any of the registers?
Thierry
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