On 04/19/2016 10:19 AM, Laxman Dewangan wrote:
On Tuesday 19 April 2016 09:41 PM, Stephen Warren wrote:
On 04/19/2016 03:43 AM, Laxman Dewangan wrote:
NVIDIA's Tegra210 support the HW debounce in the GPIO
controller for all its GPIO pins.
Add support for setting debounce timing by implementing the
set_debounce callback of gpiochip.
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
@@ -327,6 +360,9 @@ static int tegra_gpio_resume(struct device *dev)
tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
+ tegra_gpio_writel(bank->dbc_cnt[p], GPIO_DBC_CNT(gpio));
+ tegra_gpio_writel(bank->dbc_enb[p],
+ GPIO_MSK_DBC_EN(gpio));
Why not just write to the "regular" register rather than the mask
register here...
There is no regular register for enabling debounce. Only masked register
exist.
Sigh. Ignore that comment then:-)
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