On Fri, Mar 04, 2016 at 10:31:45PM -0600, Rob Herring wrote:
> On Fri, Mar 04, 2016 at 05:19:31PM +0100, Thierry Reding wrote:
> > From: Thierry Reding <treding@xxxxxxxxxx>
> >
> > The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a
> > set of lanes that are used for PCIe, SATA and USB.
> >
> > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
> > ---
> > Changes in v10:
> > - clarify that the hardware documentation means something different when
> > referring to a "port" (intra-SoC connectivity)
> >
> > Changes in v9:
> > - rename UTMI -> USB2 to match hardware documentation
> > - reword according to suggestions by Stephen Warren
> > - make Tegra132 compatible string list consistent
> > - remove mailbox support
> >
> > .../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 376 +++++++++++++++++++++
> > .../pinctrl/nvidia,tegra124-xusb-padctl.txt | 5 +
> > 2 files changed, 381 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
>
> Without really understanding the h/w here, looks okay to me.
>
> Acked-by: Rob Herring <robh@xxxxxxxxxx>
>
> > +SoC include:
> > +
> > + padctl@0,7009f000 {
>
> Drop the comma. Commas should only be used if there are distinct fields.
>
> If I get my dtc patch done, these are going to start warning, so you
> might want to go fix dts files (assuming that's where this is coming
> from).
I noticed that in today's next the updated DTC already complains about a
lot of things in existing DTS files. For Tegra that's primarily the
memory node, because it has a reg property but no unit name. Any hints
as to how to solve that? I think I remember from way back that memory
was supposed to be an exception, perhaps DTC needs to be taught that?
Thierry
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