On 02/24/2016 02:11 AM, Alexandre Courbot wrote:
On T210, the sdhci controller can address more than 32 bits of address space. Failing to express this fact results in the use of bounce buffers and affects performance. Signed-off-by: Alexandre Courbot <acourbot@xxxxxxxxxx> --- I am pretty sure this one is wrong in some way, but just to get the ball rolling as the use of bounce buffers is currently quite heavy on Jetson TX1. Thierry, Stephen, could you confirm that I got the DMA masks correctly? I am not sure about the actual addressable size on TX1, and also suspect TK1 can also address more than 32 bits.
I don't actually know what the HW capabilities are. You had best track down one of NVIDIA's HW designers/integrators; hopefully the can provide all kinds of gory details.
One thing I will say: in U-Boot, we deliberately clip usable RAM size to 2GiB so that the PA of all RAM fits into 32 bits, specifically because of IO controllers that can only address 32 bits. It is possible this was only required on earlier chips and T210 fixed it though; I don't know. Equally, I suppose the restriction might only apply to a subset of IO controllers (USB would be another one relevant to U-Boot).
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