On 2/5/2016 11:17 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@xxxxxxxxxx>
>
> Commit 86c679a52294 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and
> _calc_dynamic_ramp_rate") changed the PLL divider computation logic to
> consistently use P-divider values from tables as real dividers rather
> than the hardware values. Unfortunately for some reason many of the
> Tegra210 clocks didn't have their tables updated (most likely an over-
> sight by me when applying the patches). This commit fixes them all up.
>
> Cc: Jon Hunter <jonathanh@xxxxxxxxxx>
> Cc: Rhyland Klein <rklein@xxxxxxxxxx>
> Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
> ---
> drivers/clk/tegra/clk-tegra210.c | 94 ++++++++++++++++++++--------------------
> 1 file changed, 47 insertions(+), 47 deletions(-)
>
Acked-by: Rhyland Klein <rklein@xxxxxxxxxx>
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