Hi Lucas, Sorry for the late reply, but in my defence, I was not in Cc of the different iterations of this series. On Mon, 2 Nov 2015 21:33:17 +0100 Lucas Stach <dev@xxxxxxxxxx> wrote: > Hi all, > > New and hopefully last round of the Tegra NAND controller driver. > I fixed some last bugs that people found during review and testing > and I think the driver is ready for merging. > > v4 fixes some minor errors in the ECC handling and makes timing > calculations a bit more conservative. Some of the comments I made on your v1 were left unanswered (and were not addressed in your new versions). Can you address them or let me know why you can't? For example, I still think your NAND controller should be represented with its own node in the DT, and all NAND devices as child nodes of the controller node. I also think you should create ECC layout dynamically instead of defining a new one for each new OOB size value. Also, could you confirm that you driver supports raw accesses (I think it does, but I'd like to be sure)? Thanks, Boris -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
