On Thu, Jan 14, 2016 at 02:24:35PM -0500, Rhyland Klein wrote: > The logic for calculating the input rate used when figuring out > the proper dynamic steps for pllx was incorrect. It is supposed to > be calculated using parent_rate / m but it was just using the parent > rate directly, therefore using the wrong step values. > > Signed-off-by: Rhyland Klein <rklein@xxxxxxxxxx> > --- > drivers/clk/tegra/clk-tegra210.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) Applied, thanks. Thierry
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