On Thu, Jan 14, 2016 at 02:24:31PM -0500, Rhyland Klein wrote: > Most PLL's don't actually have LOCK_ENABLE bits. However, most PLL's > also had that flag set, which meant that the clk code was trying to > enable locks, and inadvertantly flipping bits in other fields. > > For PLLM, ensure the correct register is used for the misc_register. > PLL_MISC0 contains the EN_LCKDET bit which should be used for enabling > the lock, and PLLM_MISC1 shouldn't be used at all. > > Lastly, remove some of the settings which would point to the EN_LCKDET > bits for some PLLs. There is no need to enable the locks, and that is > done as part of the set_defaults logic already. > > Signed-off-by: Rhyland Klein <rklein@xxxxxxxxxx> > --- > drivers/clk/tegra/clk-tegra210.c | 42 ++++++++++++++-------------------------- > 1 file changed, 14 insertions(+), 28 deletions(-) It seems like this could've been split into several patches given the three different changes above. However since they all seem to relate to the lock enable behaviour I've gone and applied this as is. Thierry
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