On 1/13/2016 9:03 AM, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Fri, Jan 08, 2016 at 01:45:14PM -0500, Rhyland Klein wrote: >> Initialize PLL_D2 to a sane rate at the start of the day. >> >> Signed-off-by: Rhyland Klein <rklein@xxxxxxxxxx> >> --- >> drivers/clk/tegra/clk-tegra210.c | 1 + >> 1 file changed, 1 insertion(+) > > There are a lot of assumptions in this commit message. I'm asking myself > why does it need to be initialized to any rate at all? Isn't it up to > the user driver to set the PLL to whatever it knows to be a sane rate? > Why is 594 MHz a sane rate? > > A good commit message should answer those questions. > Thanks. This patch came about in response to some work with suspend/resume logic in the ChromeOS kernel. In the suspend/resume patch there, it reads all clk rates and caches them in suspend, then re-sets them on resume. We hadn't been using pll_d2 at all, and its rate (when read in suspend()) came back as 0. Then in resume, we would tr to set it, clk_set_rate(pll_d2, 0) and would generate a warning/error that 0 wasn't a valid rate. As for the specific rate I chose, I simply took one off the table of supported frequencies in the clk-tegra210 code, so that it was non-zero. Since we don't support suspend/resume right now in the clk drivers, I don't think its urgent to merge this patch. I can drop in in the next rev if thats easier. -rhyland -- nvpublic -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
