On Fri, Jan 08, 2016 at 01:45:05PM -0500, Rhyland Klein wrote: > This patch set fixes some issues found with the Tegra CLK drivers > in testing. There are also a few patches which clean up the code > and fix some naming issues. > > Resending with correct email address for Mike Turquette. > > Andrew Bresticker (1): > clk: tegra: pll: Fix potential sleeping-while-atomic > > Mark Kuo (2): > clk: tegra: pll: Do not disable PLLE when under HW control > clk: tegra: pll: Fix PLLE SS config > > Rhyland Klein (6): > clk: tegra: Fix divider on VI_I2C > clk: tegra210: Remove improper flags for lock_enable > clk: tegra210: Fix naming of MISC registers > clk: tegra: Fix the misnaming of nvenc from msenc > clk: tegra210: fix pllx dyn step calculation > clk: tegra210: Initialize PLL_D2 to a sane rate > > drivers/clk/tegra/clk-pll.c | 50 +++++++++++++-------- > drivers/clk/tegra/clk-tegra-periph.c | 4 +- > drivers/clk/tegra/clk-tegra210.c | 87 +++++++++++++++--------------------- > 3 files changed, 71 insertions(+), 70 deletions(-) Rhyland, This looks like a very nice round of fixups for the clock driver. I've replied to a couple of individual patches where I thought things could be improved a little, but they're mostly minor things. Thierry
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