On 12/18/2015 8:45 AM, Jon Hunter wrote:
> The EMC clock sources for tegra210 currently incorrectly include pll_c2
> and pll_c3. However, both of these should have been pll_mb as shown in
> the TRM. If tegra210 happens to be configured such that the pll_mb is the
> default clock for the EMC, as configured by the bootloader, then this will
> cause a system hang on boot. This is because the kernel will disable the
> pll_mb when disabling unused clock as it appears to be unused when it is
> not.
>
> Also add the additional pll_p clock source for the EMC.
>
> Signed-off-by: Jon Hunter <jonathanh@xxxxxxxxxx>
> ---
> drivers/clk/tegra/clk-tegra210.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 58514c44ea83..849be30b52bf 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = {
> };
>
> static const char *mux_pllmcp_clkm[] = {
> - "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
> + "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
> + "pll_p",
> };
> #define mux_pllmcp_clkm_idx NULL
>
>
Acked-by: Rhyland Klein <rklein@xxxxxxxxxx>
-rhyland
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