On 20/11/15 17:15, Stephen Boyd wrote:
> On 11/20, Jon Hunter wrote:
>> The _clk_disable_pll() function will attempt to place a PLL into bypass
>> if the TEGRA_PLL_BYPASS is specified for the PLL and then disable the PLL
>> by clearing the enable bit. To place the PLL into bypass, the bypass bit
>> needs to be set and not cleared. Fix this by setting the bypass bit and
>> not clearing it.
>>
>> Signed-off-by: Jon Hunter <jonathanh@xxxxxxxxxx>
>> ---
>
> Fixes tag? It looks like this has been wrong from the beginning
> of time.
Yes good point.
Thierry, I see you have put this in the -next branch for tegra. Do you
want to add the following?
Fixes: 8f8f484bf355 ("clk: tegra: add Tegra specific clocks")
Jon
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