From: Bill Huang <bilhuang@xxxxxxxxxx>
This fixes two things.
- Read the correct IDDQ register
- Check the correct IDDQ bit position
Signed-off-by: Bill Huang <bilhuang@xxxxxxxxxx>
Reviewed-by: Benson Leung <bleung@xxxxxxxxxxxx>
Signed-off-by: Rhyland Klein <rklein@xxxxxxxxxx>
---
drivers/clk/tegra/clk-pll.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 61bd15f9478d..932a18ce821f 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1722,7 +1722,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
val = pll_readl_base(pll);
if (val & PLL_BASE_ENABLE)
- WARN_ON(val & pll_params->iddq_bit_idx);
+ WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
+ BIT(pll_params->iddq_bit_idx));
else {
int m;
--
1.7.9.5
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