[PATCH] clk: tegra: Fix zero comparison with unsigned in clk-dfll

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The DFLL clock driver mistakenly assigned a function result
value with negative error codes to an unsigned variable and
then tried to check for error. Fix by assigning first to
signed variable and then only to unsigned if the result was
OK.

Reported-by: Dan Carpenter <dan.carpenter@xxxxxxxxxx>
Signed-off-by: Mikko Perttunen <mperttunen@xxxxxxxxxx>
---
 drivers/clk/tegra/clk-dfll.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index 6ec64577..7aa6eac 100644
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@ -1444,10 +1444,12 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td)
 	v_max = dev_pm_opp_get_voltage(opp);
 
 	v = td->soc->min_millivolts * 1000;
-	td->i2c_lut[0] = find_vdd_map_entry_exact(td, v);
-	if (td->i2c_lut[0] < 0)
+	ret = find_vdd_map_entry_exact(td, v);
+	if (ret < 0)
 		goto out;
 
+	td->i2c_lut[0] = ret;
+
 	for (j = 1, rate = 0; ; rate++) {
 		opp = dev_pm_opp_find_freq_ceil(td->soc->opp_dev, &rate);
 		if (IS_ERR(opp))
-- 
2.1.4

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