From: Bill Huang <bilhuang@xxxxxxxxxx>
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths._
Signed-off-by: Bill Huang <bilhuang@xxxxxxxxxx>
---
drivers/clk/tegra/clk-pll.c | 12 ++++++++++++
drivers/clk/tegra/clk.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index f612a8b65651..5677a5cdd3f7 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -355,6 +355,12 @@ static int clk_pll_enable(struct clk_hw *hw)
udelay(2);
}
+ if (pll->params->reset_reg) {
+ val = pll_readl(pll->params->reset_reg, pll);
+ val &= ~BIT(pll->params->reset_bit_idx);
+ pll_writel(val, pll->params->reset_reg, pll);
+ }
+
_clk_pll_enable(hw);
ret = clk_pll_wait_for_lock(pll);
@@ -376,6 +382,12 @@ static void clk_pll_disable(struct clk_hw *hw)
_clk_pll_disable(hw);
+ if (pll->params->reset_reg) {
+ val = pll_readl(pll->params->reset_reg, pll);
+ val |= BIT(pll->params->reset_bit_idx);
+ pll_writel(val, pll->params->reset_reg, pll);
+ }
+
if (pll->params->iddq_reg) {
val = pll_readl(pll->params->iddq_reg, pll);
val |= BIT(pll->params->iddq_bit_idx);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index b009c803f277..142999f1cd24 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -217,6 +217,8 @@ struct tegra_clk_pll_params {
u32 lock_enable_bit_idx;
u32 iddq_reg;
u32 iddq_bit_idx;
+ u32 reset_reg;
+ u32 reset_bit_idx;
u32 sdm_din_reg;
u32 sdm_din_mask;
u32 sdm_ctrl_reg;
--
1.7.9.5
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