On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote: > From: Tuomas Tynkkynen <ttynkkynen@xxxxxxxxxx> > > The DFLL is the main clocksource for the fast CPU cluster on Tegra124 > and also provides automatic CPU rail voltage scaling as well. The DFLL > is a separate IP block from the usual Tegra124 clock-and-reset > controller, so it gets its own node in the device tree. > Please add devicetree@xxxxxxxxxxxxxxx to the next CC list. Peter. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
