On 10/21/2014 05:45 PM, Tomeu Vizoso wrote:
Needed to properly decode the ram code register.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@xxxxxxxxxxxxx>
---
Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
index b97b8be..e2562ed 100644
--- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
@@ -11,3 +11,6 @@ Required properties:
The second entry gives the physical address and length of the
registers indicating the strapping options.
+Optional properties:
+- nvidia,long-ram-code: boolean that tells whether the ram code is long (4 bit)
+ or short (2 bit). If not present, false.
I think just "If present, the RAM code is long (4 bit). If not, short (2
bit)" would be clearer, as the booleanness of this property is not
really present in the device tree file.
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