Re: [PATCH 3/4] host1x: mipi: Include clock lanes in mipi calibrate

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On Thu, Aug 07, 2014 at 02:11:46AM -0400, Sean Paul wrote:
> When calibrating the mipi phy, also include the clock lanes
> in the calibration.
> 
> Signed-off-by: Sean Paul <seanpaul@xxxxxxxxxxxx>
> ---
>  drivers/gpu/host1x/mipi.c | 70 +++++++++++++++++++++++++++++++++++++----------
>  1 file changed, 56 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c
> index 0af2892..80578dc 100644
> --- a/drivers/gpu/host1x/mipi.c
> +++ b/drivers/gpu/host1x/mipi.c
> @@ -49,10 +49,18 @@
>  #define MIPI_CAL_CONFIG_DSIC		0x10
>  #define MIPI_CAL_CONFIG_DSID		0x11
>  
> +#define MIPI_CAL_CONFIG_DSIAB_CLK	0x19
> +#define MIPI_CAL_CONFIG_DSICD_CLK	0x1a
> +#define MIPI_CAL_CONFIG_CSIAB_CLK	0x1b
> +#define MIPI_CAL_CONFIG_CSICD_CLK	0x1c
> +#define MIPI_CAL_CONFIG_CSIE_CLK	0x1d
> +

These registers don't seem to exist on Tegra114 and earlier. It also
seems like MIPI_CAL_CONFIG_DSIC and MIPI_CAL_CONFIG_DSID no longer exist
on Tegra124 and later. And CSIC and CSID seem to be shared with DSIB
(channel A and B) now.

So I think we'll need something more elaborate than this. It should be
differentiating between SoC revisions to allow checking for valid pad
selection when calibrating.

I'll see if I can find out what's up with the change between Tegra114
and Tegra124 regarding the DSIC and DSID pads. It looks to me like they
were merged to match the DSIA and DSIB controllers, whereas before DSIA
and DSIB were used for controller DSIA and DSIC and DSID were used for
controller DSIB.

Thierry

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