On Fri, Jul 11, 2014 at 12:12:07PM +0300, Peter De Schrijver wrote: > On Fri, Jul 11, 2014 at 06:35:56AM +0200, Viresh Kumar wrote: > > Hi Tuomas, > > > > On 11 July 2014 03:12, Tuomas Tynkkynen <ttynkkynen@xxxxxxxxxx> wrote: > > > Add a new cpufreq driver for Tegra124. Instead of using the PLLX as > > > the CPU clocksource, switch immediately to the DFLL. It allows the use > > > of higher clock rates, and will automatically scale the CPU voltage as > > > well. We also rely on the DFLL driver to determine the CPU clock > > > frequencies that the chip supports, so that we can directly build a > > > cpufreq table with the OPP library helper dev_pm_opp_init_cpufreq_table. > > > > > > This driver is a completely independent of the old cpufreq driver > > > (tegra-cpufreq), which is only used on Tegra20. > > > > > > Signed-off-by: Tuomas Tynkkynen <ttynkkynen@xxxxxxxxxx> > > > > Please reuse cpufreq-cpu0 instead of adding a new driver. Similar > > is being adopted by all platforms now: krait, mvebu, etc.. > > I don't think that's going to work? The voltage scaling is handled in hw. Do we have to handle it in hardware or can we opt to do it in software, too? Thierry
Attachment:
pgpYVXuGBxhJh.pgp
Description: PGP signature
