On 22 May 2014 17:55, Andrew Bresticker <abrestic@xxxxxxxxxxxx> wrote:
> Tegra SDHCI controllers, by default, report a base clock frequency
> of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the
> actual base clock frequency. This is because the clock rate is
> configured by the clock controller, which is external to the SD/MMC
> controller. Since the SD/MMC controller has no knowledge of how this
> clock is configured, it will simply report the maximum frequency.
> While the reported value can be overridden by setting BASE_CLK_FREQ in
> VENDOR_CLOCK_CTRL on Tegra30 and later SoCs, just set CAP_CLOCK_BASE_BROKEN
> and supply sdhci_pltfm_clk_get_max_clock(), which simply does a
> clk_get_rate(), as the get_max_clock() callback.
>
> Signed-off-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx>
> Tested-by: Stephen Warren <swarren@xxxxxxxxxx>
> Acked-by: Stephen Warren <swarren@xxxxxxxxxx>
Thanks Andrew!
Signed-off-by: Ulf Hansson <ulf.hansson@xxxxxxxxxx>
Chris, can you pick this up?
Kind regards
Ulf Hansson
> ---
> Changes from v2:
> - rebased on mmc-next
> Changes from v1:
> - fixed up commit message per Stephen's suggestions
> ---
> drivers/mmc/host/sdhci-tegra.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index 4375cd4..d93a063 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -154,13 +154,15 @@ static const struct sdhci_ops tegra_sdhci_ops = {
> .set_bus_width = tegra_sdhci_set_bus_width,
> .reset = tegra_sdhci_reset,
> .set_uhs_signaling = sdhci_set_uhs_signaling,
> + .get_max_clock = sdhci_pltfm_clk_get_max_clock,
> };
>
> static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
> .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
> SDHCI_QUIRK_SINGLE_POWER_WRITE |
> SDHCI_QUIRK_NO_HISPD_BIT |
> - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
> + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
> + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> .ops = &tegra_sdhci_ops,
> };
>
> @@ -175,7 +177,8 @@ static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
> SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
> SDHCI_QUIRK_SINGLE_POWER_WRITE |
> SDHCI_QUIRK_NO_HISPD_BIT |
> - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
> + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
> + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> .ops = &tegra_sdhci_ops,
> };
>
> @@ -191,7 +194,8 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
> SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
> SDHCI_QUIRK_SINGLE_POWER_WRITE |
> SDHCI_QUIRK_NO_HISPD_BIT |
> - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
> + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
> + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> .ops = &tegra_sdhci_ops,
> };
>
> --
> 1.9.1.423.g4596e3a
>
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