When booting secondary CPU(s) which are not yet powergated, a wrong
check lead to a timeout after 100 jiffies. With this patch, we only
delay powergating if CPUs are still not powered yet.
Signed-off-by: Stefan Agner <stefan@xxxxxxxx>
---
I happend to come accross this while working on Colibri T30 support.
Obviously, the downstream U-Boot doesn't powergate all CPUs, so
the Linux kernel always timed out when booting CPU 1 through 3...
arch/arm/mach-tegra/platsmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index eb72ae7..929d104 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -114,7 +114,7 @@ static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
/* Wait for the power to come up. */
timeout = jiffies + msecs_to_jiffies(100);
- while (tegra_pmc_cpu_is_powered(cpu)) {
+ while (!tegra_pmc_cpu_is_powered(cpu)) {
if (time_after(jiffies, timeout))
return -ETIMEDOUT;
udelay(10);
--
1.8.5.4
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