On 12/19/2013 05:49 AM, Paul Walmsley wrote: > Expose the DFLL device on the NVIDIA Tegra114 Dalmore board, and connect > the DFLL (and FCPU cluster) voltage regulator. > diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt > +NVIDIA Tegra114 DFLL clocksource data in the board DTS file > + > +Optional properties: > + > +- status : device availability -- managed by the DT integration code, not > + the DFLL driver. Should be set to "okay" if the DFLL is to be > + used on this board type. There's certainly no need to document the same DT property twice. The DT docs are about documenting the schema. If the DT author decides to split the properties between a .dtsi and a .dts file, that's irrelevant to the schema. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
