Re: [PATCH 1/5] clk: tegra: Fix clock rate computation

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On Mon, Nov 18, 2013 at 04:11:35PM +0100, Thierry Reding wrote:
> The PLL output frequency is multiplied during the P-divider computation,
> so it needs to be divided by the P-divider again before returning.
> 
> This fixes an issue where clk_round_rate() would return the multiplied
> frequency instead of the real one after the P-divider.
> 

Series Acked-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
I will squash the Tegra124 fixes in the Tegra124 series.

Cheers,

Peter.
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