The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.
Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
---
Note: The 68 MHz that they are configured to is what the downstream
kernel uses. It seems as good a default as any.
drivers/clk/tegra/clk-tegra114.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 9036a22ee5aa..ceb4477ec651 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1305,6 +1305,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 600000000, 0},
{TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
{TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
+ {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
+ {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
/* This MUST be the last entry. */
{TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
--
1.8.4.2
--
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