On Tue, Oct 29, 2013 at 01:41:58PM -0600, Stephen Warren wrote: > On 10/29/2013 08:40 AM, Thierry Reding wrote: > > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> > > What does this patch solve? A description would be nice. > > I thought that this PLL essentially was fixed; while it may have some > registers than /can/ change the rate, hasn't the HW team only > characterized it to run at the single frequency that PCIe requires, > hence SW is supposed to treat it as fixed? Peter fixed it up properly. As indicated by the HACK: tag, this was really only a workaround to make Dalmore boot again. PLLE didn't use to be marked as fixed, which seems to be the reason why we've never seen this. Thierry
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