From: Thierry Reding <thierry.reding@xxxxxxxxxxxxxxxxx>
Enable the first PCIe root port which is connected to an FPGA on the
Tamonten Evaluation Carrier and add device nodes for each of the PCI
endpoints available in the standard configuration.
Signed-off-by: Thierry Reding <thierry.reding@xxxxxxxxxxxxxxxxx>
Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
---
Changes in v2:
- remove duplicate nodes and properties defined in tegra20-tamonten.dtsi
Changes in v3:
- remove PCIe endpoint device tree nodes, all devices can be discovered
via standard PCI enumeration
arch/arm/boot/dts/tegra20-tec.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index c572c43..3ada3cb 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -32,6 +32,14 @@
};
};
+ pcie-controller {
+ status = "okay";
+
+ pci@1,0 {
+ status = "okay";
+ };
+ };
+
sound {
compatible = "ad,tegra-audio-wm8903-tec",
"nvidia,tegra-audio-wm8903";
--
1.8.1.5
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