On Fri, Jul 19, 2013 at 05:25:24PM +0800, Joseph Lo wrote: > There is a difference between GICv1 and v2 when CPU in power management > mode (aka CPU power down on Tegra). For GICv1, IRQ/FIQ interrupt lines > going to CPU are same lines which are also used for wake-interrupt. > Therefore, we cannot disable the GIC CPU interface if we need to use same > interrupts for CPU wake purpose. This creates a race condition for CPU > power off entry. Also, in GICv1, disabling GICv1 CPU interface puts GICv1 > into bypass mode such that incoming legacy IRQ/FIQ are sent to CPU, which > means disabling GIC CPU interface doesn't really disable IRQ/FIQ to CPU. > > GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not > disabled by GIC CPU interface. This is done by adding a bypass override > capability when the interrupts are disabled at the CPU interface. To > support this, there are four bits about IRQ/FIQ BypassDisable in CPU > interface Control Register. When the IRQ/FIQ not being driver by the > CPU interface, each interrupt output signal can be deasserted rather > than being driven by the legacy interrupt input. > > So the wake-event can be used as wakeup signals to SoC (system power > controller). > > To prevent race conditions and ensure proper interrupt routing on > Cortex-A15 CPUs when they are power-gated, add a CPU PM notifier > call-back to reprogram the GIC CPU interface on PM entry. The > GIC CPU interface will be reset back to its normal state by > the common GIC CPU PM exit callback when the CPU wakes up. > > Based on the work by: Scott Williams <scwilliams@xxxxxxxxxx> > > Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx> Hi Joseph, We've had a rather long-standing issue with PCIe and MSI related to LP2 on Tegra20. I wonder if that's somehow related to this. Given that this is marked as Tegra114 patch explicitly I suppose not, but it certainly sounds very similar to the description above. Thierry
Attachment:
signature.asc
Description: Digital signature
