On Sun, Jun 23, 2013 at 10:21:07PM -0600, Stephen Warren wrote: > On 06/22/2013 04:45 AM, Thierry Reding wrote: > > On Fri, Jun 21, 2013 at 02:23:52PM -0600, Stephen Warren wrote: > >> From: Stephen Warren <swarren@xxxxxxxxxx> > >> > >> Beaver's PCIe lane configuration most closely matches x2 x2 x2 > >> rather than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 > >> and 5 are used, and the only way those align is with a x2 x2 x2 > >> configuration. > > > > Looking at the schematics again I have to agree. Thanks for > > catching this. > > > >> Also, disable root port 1; there's nothing connected to it. Root > >> port 0 is the on-board PCIe Ethernet, and port 2 is the mini-PCIe > >> slot. > >> > >> Signed-off-by: Stephen Warren <swarren@xxxxxxxxxx> --- This is to > >> be applied to Thierry's WIP PCIe driver branch. > > > > I've applied this to my tegra/next branch and will squash it into > > the Beaver patch that's already there. > > > > You mention another fix that might be required for PCIe on Tegra30 > > (additional write to the PADS_REFCLK_CFG1) register. Did that turn > > out to fix communication of the third port? > > Yes, I have the 3rd port working. I'm just waiting on some internal IP > review in order to say something more useful in the commit description > than "here's an opaque register write that fixes something". Perhaps you should say something more useful in the comment rather than the commit message, given that I'll probably squash the patch into one of the others before submitting. Thierry
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